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Dr. Rajeev Barua

Current Position

Professor, Dept. of Electrical and Computer Engineering

University of Maryland, College Park

Visiting Faculty, Plaksha Technology Leaders Program

Education

Ph.D. & M.S. (MIT) 

B.Tech. (IIT Delhi)

Bio

Dr. Rajeev Barua is a Professor of Electrical and Computer Engineering at the University of Maryland. Dr. Barua's research interests are in the areas of compilers, binary rewriters, embedded systems, and computer architecture. He has published over 60 peer-reviewed publications, and holds four granted patents. He is also the Founder of CEO of SecondWrite Inc, which markets a malware detection tool based on his research, where he has raised over $2M in public and private investment, and launched a product with several paying customers. Dr. Barua is a recipient of the NSF CAREER award in 2002, the UMD George Corcoran Award for teaching excellence in 2003, and the UMD Jimmy Lin Award for innovation in 2014.


Research Interests:


His research interests are in compilers both for embedded and general-purpose systems, as well as computer security. Specific current interests include:


Binary rewriting This effort is concerned with how to rewrite binaries with the least amount of restrictions, and in the most general manner. 

Support: This project is partially supported by National Science Foundation (NSF) grants #0720683 and #0916903.

 

Automatic parallelization. This project aims to automatically convert serial programs into parallel programs.

Support: This project is partially supported by the Defense Advanced Research Projects Agency (DARPA) under an AACE contract. This 2-page brochure outlines the project.

 

Compilation for fine-grained architectures. Supporting pre-fetching and nested parallelism in a compiler for the XMT machine, a fine-grained architecture being built at UMD.

Support: This project is partially supported by National Science Foundation grant #0834373.

 

Memory management for embedded systems. How to allocate data and instructions in embedded systems to specific memories such as scratch-pad memories and lockable caches.

Support: This project is partially supported by National Science Foundation (NSF) grant #0720683, and in the past by NSF grants #0133519 and #0410565.

 

Security policy enforcement. How to enforce security policies and access restrictions using a binary rewriter.


Patents:


Rajeev Barua and Sumesh Udayakumaran. “Compiler-driven dynamic memory allocation

methodology for scratch-pad based embedded systems." United States Patent #7,367,024,

Issued April 29, 2008.


• Matthew Smithson and Rajeev Barua. “Binary Rewriting without Relocation Information.”

United States Patent #8,510,723, Issued August 13, 2013.


• Aparna Kotha and Rajeev Barua. “Automatic parallelization using binary rewriting.” United

States Patent # 8,645,935. Issued February 4, 2014.


• Rajeev Barua, Kapil Anand, and Aparna Kotha. Binary Rewriting System. USPTO

provisional patent # 61930133, January 2014.


• Rajeev Barua, Kapil Anand, and Aparna Kotha. System to discover and analyze evasive

malware. USPTO provisional patent # 61932876, January 2014.



Awards:


He was awarded the 2014 Jimmy Lin Award for Innovation for his US patent #8,510,723 by

the Clark School of Engineering and the Department of Electrical and Computer

Engineering, along with his co-inventor and graduate student, Matthew Smithson. The

award carried a cash prize of $4000. The patent is titled “Binary Rewriting without relocation

Information.”


• In 2014, he was the faculty mentor for the winning team of undergraduate students at the IBM Watson case business plan competition organized by the UMD Smith School of business. He helped them with the concept of the business, and the preparation of the business plan.


• In 2013, his 1999 paper on "Parallelizing Applications into Silicon" was selected among the

most significant 25 papers in the first 20 years of the International IEEE Symposium on

Field-Programmable Custom Computing Machines. The citation said:

“This 1999 paper was well ahead of its time, identifying and solving several issues that lead

to a promising synthesis flow.”